When "make" is invoked, it builds the first target listed in the Makefile, which is typically the project executable in its default configuration.
A Makefile is a plain text file that contains a set of rules.
Each rule is of the form:
target: prerequisites ... commands to build target from prerequisites ...
If one of the prerequisite files specified by a rule doesn’t exist, make attempts to build that prerequisite from another rule that specifies the prerequisite as its target.
Once a target is built, it will not be rebuilt by subsequent invocations of make unless a prerequisite is modified (and, thus, making the target out of date).
"make" allows a Makefile to assign variables with the syntax “var = value”, and substitution of variables into rules with the syntax “$(var)”. Variable assignments may be overridden
on the “make” command line. For example, most Makefiles assign the CC variable to gcc as the default compiler and write compile rules using “$(CC)” to invoke it. If you wanted to substitute the default compiler with the avr-gcc cross compiler, you would execute “make CC=avr-gcc” instead of “make”.
"make" automatically assigns the variables $@, $<, and $^ when evaluating commands for a rule:$@ is assigned the file name of the target, $< is assigned the filename of the first prerequisite, and$^ is assigned a string consisting of the filenames of all the prerequisites with spaces between them. This feature allows the rule:
foo.o: foo.c common.h gcc -c -Wall -Werror -o foo.o foo.c
to be simplified to:
foo.o: foo.c common.h gcc -c -Wall -Werror -o $@ $<
A pattern rule is an ordinary rule that specifies a target, prerequisite, and commands for building the target, except that the file names for the target and prerequisite contain a wildcard (“%”) that matches at the beginning of the file name. Pattern rules define how to build files of a certain type. For example, the following pattern rule specifies how to build an object file from any C source-file:
%.o: %.c gcc -c -Wall -Werror -o $@ $<
A Makefile is a plain text file that contains a set of rules.
Each rule is of the form:
target: prerequisites ... commands to build target from prerequisites ...
If one of the prerequisite files specified by a rule doesn’t exist, make attempts to build that prerequisite from another rule that specifies the prerequisite as its target.
Once a target is built, it will not be rebuilt by subsequent invocations of make unless a prerequisite is modified (and, thus, making the target out of date).
"make" allows a Makefile to assign variables with the syntax “var = value”, and substitution of variables into rules with the syntax “$(var)”. Variable assignments may be overridden
on the “make” command line. For example, most Makefiles assign the CC variable to gcc as the default compiler and write compile rules using “$(CC)” to invoke it. If you wanted to substitute the default compiler with the avr-gcc cross compiler, you would execute “make CC=avr-gcc” instead of “make”.
"make" automatically assigns the variables $@, $<, and $^ when evaluating commands for a rule:$@ is assigned the file name of the target, $< is assigned the filename of the first prerequisite, and$^ is assigned a string consisting of the filenames of all the prerequisites with spaces between them. This feature allows the rule:
foo.o: foo.c common.h gcc -c -Wall -Werror -o foo.o foo.c
to be simplified to:
foo.o: foo.c common.h gcc -c -Wall -Werror -o $@ $<
A pattern rule is an ordinary rule that specifies a target, prerequisite, and commands for building the target, except that the file names for the target and prerequisite contain a wildcard (“%”) that matches at the beginning of the file name. Pattern rules define how to build files of a certain type. For example, the following pattern rule specifies how to build an object file from any C source-file:
%.o: %.c gcc -c -Wall -Werror -o $@ $<
